| Papers List | (1981-2008) | ||||||
| Date | Level | Review | Author(s) | Title | Paper infromation | ||
| 2010 | Domestic | Masayuki Kobayashi, Wataru Sendo, Masahiko Toyonaga, Michiaki Muraoka | Dynamic Analysis Method with Consideration of Delay Time Variation by Crosstalk | TRICK(Technical Report on Infromation and Computer Scienece from Kochi), Vol2. No.3, March 2010. | |||
| 2010 | Domestic | Masahiko Toyonaga, Masahiro Kurusu, Upul Herath | A Study of Routing Algorithms for Next Generation System-in-Package | TRICK(Technical Report on Infromation and Computer Scienece from Kochi), Vol2. No.6, March 2010. | |||
| 2010 | Domestic | Kiyoshi Sugimoto, Haruka Miyagi, Yuma Yoshida, Michiaki Muraoka, Masahiko Toyonaga | A Method of Optimal ECO Design Stage Decision in SoC Design Flow | TRICK(Technical Report on Infromation and Computer Scienece from Kochi), Vol2. No.7, March 2011. | |||
| 2009 | Domestic | Kazuo Hosogi, Masahiro Kurusu, Masahiko Toyoanga | Clock Skew Evaluation of Triplet Tree Structure by 45-degree Routing 1−16 | the 2009 Shikoku-section Joint Convention of the Institutes of Electrical and related Engineers.(26.Sep.2009) | |||
| 2009 | Domestic | Shota Terada, Yuma Yoshida, Michiaki Muraoka, Masahiko Toyoanga | Crosstalk Avoidance Placement by Estimating Wire Shapes1−17 | the 2009 Shikoku-section Joint Convention of the Institutes of Electrical and related Engineers.(26.Sep.2009) | |||
| 2009 | Domestic | Kiyoshi Sugimoto, Haruka Miyagi, Yuma Yoshida, Masahiko Toyonaga | A Method of Optimal ECO Design Stage Decision in SoC Design Flow1-18 | the 2009 Shikoku-section Joint Convention of the Institutes of Electrical and related Engineers.(26.Sep.2009) | |||
| 2009 | Domestic | Masayuki Kobayashi, Masahiko Toyonaga, Michiaki Muraoka | Dynamic Analysis Method with Consideration of Delay Time Variation by Crosstalk 9-3 | the 2009 Shikoku-section Joint Convention of the Institutes of Electrical and related Engineers.(26.Sep.2009) | |||
| 2009 | Domestic | Wataru Sendo, Masayuki Kobayashi, Masahiko Toyonaga, Michiaki Muraoka | Delay Time Evaluation of Crosstalk 9-4 | the 2009 Shikoku-section Joint Convention of the Institutes of Electrical and related Engineers.(26.Sep.2009) | |||
| 2009 | Domestic | ○ | Haruka Miyagi, Yuma Yoshida, Michiaki Muraoka, Masahiko Toyonaga | Layout Placement ECO Effectiveness Evaluation Method | Proc of DA Symposium 2008, IPSJ,Vol.2009, pp.67-72,Aug.,2009 | ||
| 2009 | Inter-national | ◎ | Xin Zhang, Yuma Yoshida, and Masahiko Toyonaga | XIN:Fast Wirelength Estimation Algorithm for Placement in VLSI Design | ISDLT09, pp.61-64, May 2009. | ||
| 2009 | Inter-national | ◎ | Xin Zhang, Tsuyoshi Takeuchi, and Masahiko Toyonaga | AKEBONO: A Novel Quick Incremental Placer | International Conference on IC Design and Technology (ICICDT09),pp51-53, May 2009. | ||
| 2009 | Inter-national | ◎ | Xin Zhang, Tsuyoshi Takeuchi, and Masahiko Toyonaga | Cell Merge: A Basic-Pre-Clustering Clustering Algorithm for Placement | International Conference on IC Design and Technology (ICICDT09),pp47-50, May 2009. | ||
| 2009 | Inter-national | ◎ | Raveen R. Goundar, Ken-ichi Shiota, and Masahiko Toyonaga | A Novel Method for Elliptic Curve Multi-Scalar Multiplication | International Journal of Applied Mathematics and Computer Sciences, vol. 4, no.9, pp. 1-5, 2009. | ||
| 2009 | Domestic | Haruka Miyagi, Masahiko Toyonaga | A Study of Placement Optimization by Evaluating Full Permutation of Partial Elements | TRICK(Technical Report on Infromation and Computer Scienece from Kochi), Vol.1 No.7, March 2009. | |||
| 2009 | Domestic | Shuhei Yokoyama, Hikaru Ebie, Masahiko Toyonaga | A Study of Equivalent Points to Grouped Clock Input Terminals 1-10 | TRICK(Technical Report on Infromation and Computer Scienece from Kochi), Vol1. No.6, March 2009. | |||
| 2008 | Domestic | Haruka Miyagi, Yuma Yoshida, Masahiko Toyonaga | A Placement Optimization using Partial Full Permitation Search Method 1-9 | the 2008 Shikoku-section Joint Convention of the Institutes of Electrical and related Engineers.(27.Sep.2008) | |||
| 2008 | Domestic | Shuhei Yokoyama, Hikaru Ebie, Masahiko Toyonaga | A Study of Equivalent Points to Grouped Clock Input Terminals 1-10 | the 2008 Shikoku-section Joint Convention of the Institutes of Electrical and related Engineers.(27.Sep.2008) | |||
| 2008 | Domestic | Masahiro Kurusu, Masahiko Toyonaga | Multi-Layer Router using Octalinear Directions 1-11 | the 2008 Shikoku-section Joint Convention of the Institutes of Electrical and related Engineers.(27.Sep.2008) | |||
| 2008 | Domestic | Wataru Sendo, Masayuki Kobayashi, Masahiko Toyonaga, Michiaki Muraoka | Cross-talk Analysis Method using Logic Test Pattern 9-7 | the 2008 Shikoku-section Joint Convention of the Institutes of Electrical and related Engineers.(27.Sep.2008) | |||
| 2008 | Domestic | Katsuya Ishiguro, Takuya Saito, Masato Sasaki, Masahiko Toyonaga | Mobile Equipment Monitoring system in Kochi University 16-19 | the 2008 Shikoku-section Joint Convention of the Institutes of Electrical and related Engineers.(27.Sep.2008) | |||
| 2008 | Domestic | Takuya Saito, Katsuya Ishiguro, Masato Sasaki, Katsuhiko Sannomiya, Tomomitsu Yuki, Masahiko Toyonaga | Assurance DHCP system introduced in Kochi University 16-20 | the 2008 Shikoku-section Joint Convention of the Institutes of Electrical and related Engineers.(27.Sep.2008) | |||
| 2008 | Domestic | Upul Herath, Michiaki Muraoka, Masahiko Toyonaga | ORCA: An Octalinear Router for Crosstalk Avoidance 17-46 | the 2008 Shikoku-section Joint Convention of the Institutes of Electrical and related Engineers.(27.Sep.2008) | |||
| 2008 | Domestic | 斎藤 卓也, 中里 一仁, 石黒 克也, 佐々木 正人, 三宮, 克彦, 結城 朝光, 豊永 昌彦 | 高知大学における全学認証DHCP システムの導入 | 第12回学術情報処理研究集会論文集,Sep.,pp.131-134, 2008. | |||
| 2008 | Domestic | Yes | Masayuki Kobayashi, Masahiko Toyonaga, Michiaki Muraoka | Crosstalk Analysis Method with consideration of Dynamic Behaviour | Proc of DA Symposium 2008, IPSJ,Vol.2008, No.7, pp.127-132,Aug.,2008. | ||
| 2008 | Domestic | Yes | Yuma Yoshida, Masahiko Toyonaga, Michiaki Muraoka | A Placement Objective Function for Crosstalk Avoidance | Proc of DA Symposium 2008, IPSJ, Vol.2008, No.7, pp.61-66,Aug.,2008. | ||
| 2008 | Inter-national | Yes | Raveen Ravinesh Goundar, Ken-ichi Shiota, Masahiko Toyonaga | SPA Resistant Scalar Multiplication using Golden Ratio Addition Chain Method | IAENG International Journal of Applied Mathematics, vol. 38, issue 2, pp. 83-88, Jun. 2008 | ||
| 2008 | Inter-national | Yes | Raveen Ravinesh Goundar, Ken-ichi Shiota, Masahiko Toyonaga | New Strategy for Doubling-Free Short Addition-Subtraction Chain | Applied Matematics & Information Sciences - An International Journal, Vol2, No.2,pp123-133. May 2008. | ||
| 2007 | Inter-national | Yes | Tingyuan Nie, Masahiko Toyonaga | An Efficient and Reliable Watermarking System for IP Protection | IEICE Trans. Fundamentals E90-A, No.9, pp.1932-1939, Sep. 2007 | ||
| 2007 | Domestic | T.Takeuchi, S.Bando， X..Zhang, M.Toyonaga | A Very Fast Placement Method based on Net-list Connectivity 1-1 | the 2007 Shikoku-section Joint Convention of the Institutes of Electrical and related Engineers.(29.Sep.2007) | |||
| 2007 | Domestic | Yuma Yoshida, Tingyuan Nie, Masahiko Toyonaga | A Study of Crosstalk Avoidance Driven Placement 1-2 | the 2007 Shikoku-section Joint Convention of the Institutes of Electrical and related Engineers.(29.Sep.2007) | |||
| 2007 | Domestic | Akira Taketani, Xian Fang, Masahiko Toyonaga | A Maze Routing Method for Crosstalk Avoidance 1-3 | the 2007 Shikoku-section Joint Convention of the Institutes of Electrical and related Engineers.(29.Sep.2007) | |||
| 2007 | Domestic | M.Watanabe, Y.Ikeno, M.Toyonaga | A Straight Line Oriented Maze Routing with Obstacle Avoidance 1-4 | the 2007 Shikoku-section Joint Convention of the Institutes of Electrical and related Engineers.(29.Sep.2007) | |||
| 2007 | Domestic | H.Ebie, H.Shimokawa, M.Toyonaga | A Clock-Tree Generation based on Triplet-terminals 1-5 | the 2007 Shikoku-section Joint Convention of the Institutes of Electrical and related Engineers.(29.Sep.2007) | |||
| 2007 | Domestic | H.Shimokawa, H.Ebie, M.Toyonaga | A Study of Wire-lengths for Binary and Triplet Clock Trees 1-6 | the 2007 Shikoku-section Joint Convention of the Institutes of Electrical and related Engineers.(29.Sep.2007) | |||
| 2007 | Domestic | H.Gao, M.Kobayashi, M.Toyonaga, M.Muraoka | Crosstalk Detection Method by Logic Simulator 9-17 | the 2007 Shikoku-section Joint Convention of the Institutes of Electrical and related Engineers.(29.Sep.2007) | |||
| 2007 | Domestic | M.Kobayashi, H.Gao, M.Toyonaga, M.Muraoka | Crosstalk Detection Prototype System by Logic Simulator 9-18 | the 2007 Shikoku-section Joint Convention of the Institutes of Electrical and related Engineers.(29.Sep.2007) | |||
| 2007 | Domestic | Raveen Ravinesh Goundar, Kenn'ichi Shiota, Masahiko Toyonaga |
Efficient
and Secure Scalar Multiplication for Pairing-Based Cryptosystems 17-24 |
the 2007 Shikoku-section Joint Convention of the Institutes of Electrical and related Engineers.(29.Sep.2007) | |||
| 2007 | Domestic | A.Okamoto T.Saito M.Sasaki M.Toyonaga | Stable Service and Users Activity of the Integrated Information System in Kochi University 16-29 | the 2007 Shikoku-section Joint Convention of the Institutes of Electrical and related Engineers.(29.Sep.2007) | |||
| 2006 | Inter-national | Yes | DongQing Wang, Masahiko Toyonaga, |
A Certain SA Solver TOSA for Global Placement | Proc. of IEEE Asia Pacific
Conference on Circuit and System (APCCAS 2006), pp.485-488(Dec., 2006) |
||
| 2006 | Domestic | Xin Zhang， Masahiko Toyonaga |
A Two-Dimensional Placement by Pair of One-Dimensional SA Solutions | the 2006 Shikoku-section Joint Convention of the Institutes of Electrical and related Engineers.17-8(27.Sep.2006) | |||
| 2006 | Domestic | Yoske Ikeno, Shuji Bando, Masahiko Toyonaga | A Method of Straight Forward Maze Routing | the 2006 Shikoku-section Joint Convention of the Institutes of Electrical and related Engineers.1-2(27.Sep.2006) | |||
| 2006 | Domestic | Xi Xang, Shuji Bando, Masahiko Toyonaga | A Quick Placement Method using Net-list Graph | the 2006 Shikoku-section Joint Convention of the Institutes of Electrical and related Engineers.1-3(27.Sep.2006) | |||
| 2006 | Domestic | Han Xang, Tingyuan Nie, Masahiko Toyonaga | A Wire Length Estimation Method for Multi-terminal Net | the 2006 Shikoku-section Joint Convention of the Institutes of Electrical and related Engineers.1-4(27.Sep.2006) | |||
| 2006 | Domestic | Shunsuke Tanimoto, Yuki Yamamoto, Masahiko Toyonaga | A Cross-talk aware Maze Routing Method | the 2006 Shikoku-section Joint Convention of the Institutes of Electrical and related Engineers.1-5(27.Sep.2006) | |||
| 2006 | Domestic | Masato Yokoyama, Shuu Shiroma, Masahiko Toyonaga, Shigeo Kuninobu | Design of Floating Point Unit for Graphic Processing | the 2006 Shikoku-section Joint Convention of the Institutes of Electrical and related Engineers.10-1(27.Sep.2006) | |||
| 2006 | Domestic | Masashi Nanbu, Ayumi Okamoto, Masato Sasaki, Masahiko Toyonaga, Tokiyo Ozaki | The LDAP-based Authentication and Authorization Infrastructure for the Integrated Information System in Kochi University | the 2005 Shikoku-section Joint Convention of the Institutes of Electrical and related Engineers. 16-7(28.Sep.2005) | |||
| 2005 | Domestic | Shuji Bando, Kazuyuki Tanabe, Masahiko Toyonaga, Shigeo Kuninobu | The Iteration Number of Heat-Equilibrium Simulation and the Quality of Solutions in Simulated Annealing Method | the 2005 Shikoku-section Joint Convention of the Institutes of Electrical and related Engineers.1-21(28.Sep.2005) | |||
| 2005 | Domestic | Hiroyuki Jinnwo, Chiyo Matsudani, Masashi Yamazaki, Masahiko Toyonaga | A Study of Supersonic Wave Movement Sensor for Sleep Appearance Data Sampling | the 2005 Shikoku-section Joint Convention of the Institutes of Electrical and related Engineers. 1-22(28.Sep.2005) | |||
| 2005 | Domestic | Chiyo Matsudani, Hiroyuki Jinnwo, Masashi Yamazaki, Masahiko Toyonaga | Sleep Appearance Data Recording System by usign Supersonic Wave Movement Sensor | the 2005 Shikoku-section Joint Convention of the Institutes of Electrical and related Engineers. 1-23(28.Sep.2005) | |||
| 2005 | Domestic | Takuro Tsutsui, Yanson Cho, Masahiko Toyonaga | A Benchmark Experiments of Floor-planning Model based on Block Tile Model | the 2005 Shikoku-section Joint Convention of the Institutes of Electrical and related Engineers. 9-1(28.Sep.2005) | |||
| 2005 | Domestic | Yuki Yamamoto, Masashi Yamazaki, Masahiko Toyonaga, Shigeo Kuninobu | A Study of Wire Congestion oriented Incremental Placement | the 2005 Shikoku-section Joint Convention of the Institutes of Electrical and related Engineers. 9-2(28.Sep.2005) | |||
| 2005 | Domestic | Hideki Suwa, Shigeru Takenaga, Masahiko Toyonaga | A Study of HV-Free Maze Re-routing for Specified Layers | the 2005 Shikoku-section Joint Convention of the Institutes of Electrical and related Engineers. 9-3(28.Sep.2005) | |||
| 2005 | Inter-national | Yes | Tingyuan Nie, Tomoo Kisaka, Masahiko Toyonaga |
A Watermarking System for IP Protection by a Post Layout Incremental Router | 42nd Design Automation Conference, pp.218-221(June, 2005) | ||
| 2005 | Inter-national | Yes | Tingyuan Nie, Tomoo Kisaka, Masahiko Toyonaga |
A Post Layout Watermarking Method for IP Protection | 2005 IEEE International Symposium on Circuit and Systems(ISCAS) Proceedings, pp6206-6209(May, 2005) | ||
| 2005 | Domestic | Kazuyuki Tanabe, Masahiko Toyonaga | A Placement Optimization by Simulated Annealing using Various Cooling Schedule | IEICE Technical Report VLD2005-6,pp.1-6(20 May,2005) | |||
| 2005 | Domestic | Shigeru Takenaga, Masahiko Toyonaga | A Multi-Layer Incremental Router for Layout Design with Fewer Layers | IEICE Technical Report VLD2005-6,pp.7-12(20 May,2005) | |||
| 2004 | Domestic | Yes | Masahiko Toyonaga, Masashi Yamazaki, Keiichi Kurokawa, Shigeo Kuninobu | Net Wire Length Certified Re-Placement for Standard-Cell | Proc of DA Symposium 2004, IPSJ, Vol.2004, No.8, pp.109-114. | ||
| 2004 | Domestic | Yes | Masahiko Toyonaga, Shigeru Takenaga, Shigeo Kuninobu | A Study of Simple Multi-layer Maze Router for Incremental Layout Design | Proc of DA Symposium 2004, IPSJ, Vol.2004, No.8, pp.115-120. | ||
| 2004 | Domestic | Shinpei Kojima, Masahiko Toyonaga | A Study of Cost Function for the Global Wiring Optimization | the 2004 Shikoku-section Joint Convention of the Institutes of Electrical and related Engineers. 1-19(26.Sep.2004) | |||
| 2004 | Domestic | Genki Ryu, Shinpei Kojima, Masahiko Toyonaga | A Global Routing Method with Redundant Path | the 2004 Shikoku-section Joint Convention of the Institutes of Electrical and related Engineers. 1-20(26.Sep.2004) | |||
| 2004 | Domestic | Dong Qing Wang, Shinpei Kojima, Masahiko Toyonaga | A Study of Fractal Dimetional Analysis for Stanard-Cell Circuit | the 2004 Shikoku-section Joint Convention of the Institutes of Electrical and related Engineers. 1-21(26.Sep.2004) | |||
| 2004 | Domestic | Yangson Cho, Masahiko Toyonaga, Shigeo Kuninobu | A Floor-planning Model base on Tiles | the 2004 Shikoku-section Joint Convention of the Institutes of Electrical and related Engineers. 1-22(26.Sep.2004) | |||
| 2004 | Domestic | Kazuyuki Tanabe, Masahiko Toyonaga | A Study of Relationship between Cooling Process and Final Solutions in Simulated Annealing Method | the 2004 Shikoku-section Joint Convention of the Institutes of Electrical and related Engineers. 1-24(26.Sep.2004) | |||
| 2004 | Domestic | Gi Wang, Masahiko Toyonaga | A Study of Simulated Annealing with Multipul-Cooling Schedule | the 2004 Shikoku-section Joint Convention of the Institutes of Electrical and related Engineers. 1-25(26.Sep.2004) | |||
| 2004 | Domestic | Arito Katsurada, Tingyuan Nie, Masahiko Toyonaga | A Faster DES Cryptography Program using a Table Method | the 2004 Shikoku-section Joint Convention of the Institutes of Electrical and related Engineers. 1-29(26.Sep.2004) | |||
| 2004 | Domestic | Masato Yokoyama, Katsunori Miyahara, Kazuki Maeda, Masahiko Toyonaga, Shigeo Kuninobu | Comparing the Performance of Redundant-Binary-Adder and Binary-Adder | the 2004 Shikoku-section Joint Convention of the Institutes of Electrical and related Engineers. 10-6 (26.Sep.2004) | |||
| 2004 | Domestic | Kazuki Maeda, Manabu Tahara, Tomokazu Masuda, Masahiko Toyonaga, Shigeo Kuninobu | Floating Point Accelerator Design using Verilog HDL | the 2004 Shikoku-section Joint Convention of the Institutes of Electrical and related Engineers. 10-7(26.Sep.2004) | |||
| 2004 | Domestic | Toshiro Akino, Tomoki Nakatani, Masahiko Toyonaga | Global Placement Optimization for Standard Cells in a Large Scale Block based on Simulated Annealng Method | Memoirs of the scholol of B.O.S.T of Kinki University, No.14, pp.49-62(2004) | |||
| 2003 | Inter-national | Yes | Masahiko Toyonaga, Keiichi Kurokawa, Toshiro Akino, Shigeo Kuninobu | Cell Placement Optimization using Phase Transition and Annealing by a Metropolis's Monte-Carlo Simulation | Proceedings of SASIMI (Workshop on Syntehsis And System Integration of Mixed Information Technologies)2003, April 2003 Hiroshima, pp95-101. | ||
| 2003 | Domestic | Tomoki Nakatani, Toshiro Akino, Masahiko Toyonaga | Study on the Accuracy of an Approximate Cell Position by Global Placement Usin Simulated Annealing | IEICE Technical Report VLD2003-28, pp101-106, June 2003. | |||
| 2003 | Domestic | T.Lee, N.Hayashi, S.Machida, T.Fujii, M.Toyonaga, S.Kuninobu | A High-Speed Multiplier using Redundant Representation with Verilog-HDL | the 2003 Shikoku-section Joint Convention of the Institutes of Electrical and related Engineers.10-11(12.Oct.2003) | |||
| 2003 | Domestic | K.Maeda, N.Miyaji, K.Yamaguchi, Y.Yamanaka, M.Toyonaga, S.Kuninobu | CPU Core Design using Verilog HDL | the 2003 Shikoku-section Joint Convention of the Institutes of Electrical and related Engineers.10-12(12.Oct2003) | |||
| 2003 | Domestic | Masashi Yamazaki, Masahiko Toyonaga | A Wire-load oriented Incremental Standard-cell Placement Approach | the 2003 Shikoku-section Joint Convention of the Institutes of Electrical and related Engineers. 1-10(12.Oct.2003) | |||
| 2003 | Domestic | Shigeru Takenaga, Masahiko Toyonaga | An Incremental Single Net Multi-Layer Re-Router | the 2003 Shikoku-section Joint Convention of the Institutes of Electrical and related Engineers. 1-12(12.Oct.2003) | |||
| 2003 | Domestic | Yansong Cho, Masahiko Toyonaga, Shigeo Kuninobu | A Study of the Initial Temperature Dependence of Placement using Simulated Annealing | the 2003 Shikoku-section Joint Convention of the Institutes of Electrical and related Engineers. 1-3(12.Oct.2003) | |||
| 2003 | Domestic | Kazuyuki Tanabe, Masahiko Toyonaga, Shigeo Kuninobu | A Study of Combined Optimization Method of Pire-wise Exchange and Simulated Annealing | the 2003 Shikoku-section Joint Convention of the Institutes of Electrical and related Engineers. 1-4(12.Oct.2003) | |||
| 2003 | Domestic | Tomoo Kisaka, Tingyuan Nie, Masahiko Toyonaga | A Special Redundant Knob Router for Water-Marking | the 2003 Shikoku-section Joint Convention of the Institutes of Electrical and related Engineers. 1-11(12.Oct.2003) | |||
| 2003 | Domestic | Tingyuan Nie, Masahiko Toyonaga, Kenn-ichi Shiota | A LSI-Layut Water-Marking Method using A Special Router | the 2003 Shikoku-section Joint Convention of the Institutes of Electrical and related Engineers. 9-11(12.Oct.2003) | |||
| 2002 | Domestic | Yes | Takuya Yasui, Keiichi Kurokawa, Masahiko Toyonaga, Atsushi Takahasi | A circuit optimization method by the register path modification in consideration of the range of feasible clock timing | Proceedings of IPSJ DA Symposium, Vol.2002, No.10, pp.259-264 | ||
| 2002 | Inter-national | Yes | Keiichi Kurokawa, Takuya Yasui, Yoichi Matsumura, Masahiko Toyonaga, Atsushi Takahashi | A High-Speed and Low-Power Clock Tree Synthesis by Dynamic Clock Scheduling | Transaction of IEICE, Vol.E, 2002 to be published | ||
| 2001 | Inter-national | Yes | Keiichi Kurokawa, Takuya Yasui, Masahiko Toyonaga, Atsushi Takahasi | A Practical Clock Tree Synthesis for Semi-Synchronous Circuits | Transaction of IEICE, Vol.E84-A No.11 pp.2705-2713 2001 | ||
| 2000 | Inter-national | Yes | Masahiko Toyonaga, Keiichi Kurokawa, Takuya Yasui, Atsushi Takahasi | A Practical Clock Tree Synthesis for Semi-Synchronous Circuits | Proceedings of International Symposium on Physical Desing, pp.159-164, 2000. | ||
| 2000 | Domestic | Yes | Yasui, Kurokawa, Toyonaga, Takahashi | Semi-synchronous clock tree generation by dynamic clock scheduling | Proceedings of IPSJ DA Symposium, Vol.2000,No.8, pp.43-48 | ||
| 2000 | Domestic | Masahiko Toyonaga | ISPD2000 Report | IEICE-VLD,2000 | |||
| 2000 | Domestic | Yes | Shunji Saika, Masahiro Fukui, Masahiko Toyonaga, Toshiro Akino | WSSA:A high performance simulated annealing and its application to transistor placement | Transaction of IEICE, Vol.E 83-A, No.12, December, 2000, pp.2584-2591 | ||
| 1999 | Domestic | Yes | Keiichi Kurokawa, Noriko Ishibashi, Masahiko Toyonaga | A placement optimization by Simulated Phase Transition method | Proceedings of the 12-th Workshod on Circuit and Systems in Karuizawa, pp451-456, 1999 | ||
| 1999 | Domestic | Yes | Saika, Fukui, Ooye, Toyonaga, Akino | Transister placement optimization by annealing with simulated phase transition | DA Symposium, Aug 1999 | ||
| 1999 | Domestic | N.Ishibashi, K.Kurokawa, M.Toyonaga | Placement optimization by using simulated phase transition and simulated annealing | Technical Report of IEICE VLD98-131, May 1999, pp1-6 | |||
| 1998 | Domestic | Masahiko Toyonaga, Toshiro Akino | Placement optimization by simulated phase transition | IEICE Technical Report, VLD98-20, 1998, pp.37-44 | |||
| 1998 | Domestic | Yes | Miwaka Takahashi, Yoshihiro Seko, Minako Fukumoto, Fumihiro Kimura, Masahiko Toyonaga | A logic synthesis method based on layout wirig length estimation | Proceedings of the 11-th Workshod on Circuit and Systems in Karuizawa, 1998 | ||
| 1998 | Domestic | Yes | Saika, Fukui, Ooye, Toyonaga, Akino | Transister placement optimization by annealing with simulated phase transition | Design GAIA '98 | ||
| 1997 | Domestic | H.Shibata, K.Tsuzuki, M.Toyonaga | A method of LSI wiring layer flatten | IEICE Sogotaikai 1997-A-3- 5 | |||
| 1997 | Domestic | K.Tsuzuki, R.Yamaguchi, M.Toyonaga | A Cross-talk verification around the clock network | IEICE Sogotaikai 1997-A-3-10 | |||
| 1997 | Domestic | M.Fukumoto, F.Kimura, N.Koshita, M.Toyonaga | A wiring length estimation for fan-out numbers | IEICE Sogotaikai 1997-A-3-12 | |||
| 1996 | Domestic | Takahashi, Toyonaga, Mizuno, Yoshida, Muraoka | DSP Data-path design method by using soft-macro generatior | IEICE Sogotaikai 1996-A-101 | |||
| 1996 | Domestic | Yes | Kimura, Fukumoto, Koshita, Toyonaga | Layout estimation method based on cost-function of placement | DA-Symposium, Aug 1996, pp.177-182 | ||
| 1995 | Inter-national | Yes | Masahiko Toyonaga, Shih-Tsung Yang, Toshiro Akino, Isao Shirakawa | A new approach of fractal dimension based module clustering for VLSI layout | Proceedings of International Symposium on Circuit and System(ISCAS) 95, pp185-187 | ||
| 1994 | Domestic | Masahiko Toyonaga, Shih-Tsung Yang, Isao Shirakawa, Toshiro Akino | A new approach of fractal dimension based module clustering for VLSI layout | IEICE Technical Report, CAS93-97, 1994, pp53-60 | |||
| 1994 | Inter-national | Yes | Masahiko Toyonaga, Shih-Tsung Yang, Toshiro Akino, Isao Shirakawa | A new approach of fractal-analysis based module clustering for VLSI layout | Transaction of IEICE, Vol.E 77-A, No.12, December, 1994, pp.2045-2052 | ||
| 1994 | Inter-national | Yes | Masahiko Toyonaga, Chie Iwasaki, Yoshiaki Sawada, Toshiro Akino | A multi-layer channel router using simulated annealing | Transaction of IEICE, Vol.E 77-A, No.12, December, 1994, pp.2085-2091 | ||
| 1992 | Inter-national | Yes | Takahiro Shiohara, Atsushi Yamamoto, Masahiko Toyonaga, Toshiro Akino | A pin assignment and global routing algorithm for floor-plannnig | Proc.of SASIMI 1992, pp424-433 | ||
| 1992 | Domestic | Masahiko Toyonaga, Shih-Tsung Yang, Toshiro Akino, Isao Shirakawa | A clustering approach based on fractal dimension analysis | IEICE Technical Report, CAS92-69, Dec 1992, pp31-38 | |||
| 1992 | Domestic | Yes | Chiye Iwasaki, Masahiko Toyonaga, Toshiro Akino | STANZA：channel routing based on the vertical constraints global minimization | Proceedings of the 5-th Karuizawa Workshod on Circuit and Systems, pp.381-386, 1992 | ||
| 1991 | Book | Masahiko Toyonaga, Hiroaki Okude, Toshiro Akino (Part of) | VLSI Logic Syntehsis and Design | ISBN4‐274‐03312‐0（Ohm Press.） | |||
| 1990 | Inter-national | Yes | Masahiko Toyonaga, Hiroaki Okude, Toshiro Akino | Circuit Partitioning by Trembling Spot-Check | IFIP Workshop on Design&Test of ASIC, 1990, pp45-47 | ||
| 1990 | Inter-national | Yes | Masahiko Toyonaga, Hiroaki Okude, Toshiro Akino | Placement and global wiring optimization by trembling spot-check | Proceedings of SASIMI 1990, pp300-307 | ||
| 1990 | Inter-national | Yes | Yoshiyuki Kawakami, Koichi Satoh, Masahiko Toyonaga, Toshiro Akino | A Topological Channel Router and Channel Compaction | Proceedings of SASIMI 1990, pp308-315 | ||
| 1990 | Domestic | Sato, Toyonaga, Kawakami, Akino | O(N) Channel Compaction Method | VLD90-4, 1990 | |||
| 1990 | Domestic | Shunji Saika, Masahiko Toyonaga | IO Peripheral routing method for Standard-Cell Layout | Sekkei Jidoka 53-4,July 1990 | |||
| 1990 | Domestic | Masahiko Toyonaga, Hiroaki Okude, Toshiro Akino | Global wiring by Trembling Spot-Check | Sekkei Jidoka 53-4,July 1990 | |||
| 1990 | Domestic | Yes | Kawakami, Sato, Toyonaga, Akino | A channel wiring method with variable width of wires | Proceedings of the 3rd Karuizawa Workshod on Circuit and Systems, pp302-309, 1990 | ||
| 1989 | Inter-national | Yes | Masahiko Toyonaga, Hiroaki Okude, Toshiro Akino | Placement optimization by trembling-spot check | Technical Digest of 1989 Internaltional Conference on VLSI and CAD, Oct 1989, pp85 | ||
| 1989 | Inter-national | Yes | Masahiko Toyonaga, Hiroaki Okude, Toshiro Akino | A placement optimization by trembling-spot check | Transaction of IEICE, Vol.E 72, No.12, p.1350-1359, 1989 | ||
| 1989 | Domestic | Akino, Toyonaga, Okude | A study of placement algorithm based on nagnetic field approximation | CAS88-100, Feb 1989, pp.17-24 | |||
| 1989 | Domestic | Hiroaki Okude, Masahiko Toyonaga, Toshiro Akino | A study of evaluation function for standard-cell placement | Technical Report of IEICE VLD89-93, Feb 1989, pp17-24 | |||
| 1989 | Domestic | Yes | Akino, Toyonaga, Okude, Horiuchi | A study of placement optimization method for Sea of Gate Approach | Proccedings of th 2nd Karuizawa Workshop on Circuit and System,1989 | ||
| 1988 | Domestic | Yes | Taguchi, Kitagawa, Okude, Toyonaga, Chimura, Akino | STELLA2 Floor-planning based on Simulated Annealing | DA Symposium, Aug 1988 | ||
| 1987 | Domestic | M.Toyonaga, T.Akino | Placement Improvement by Fast Annealed Simulation Techniqu | Technical Report of IEICE CAS86-192, Jan 1987, pp33-38 | |||
| 1986 | Inter-national | Yes | Y.Myatake, M.Yamada, JJ.Kim, O.Nagai, M.Toyonaga | On the implementation of the heat bath algorithm for Monte-Carlo simulations of classical Heisenberg spin sysmtems | Journal of physics, C, Solid State Phys., 19, 1986 | ||
| 1986 | Inter-national | Yes | Y.Myatake, Y.Yamada, K.Nishino, O.Nagai, M.Toyonaga | Monte carlo studies for three-dimensional quantum-spin models | Journal of Magnetism and Magnetic Materials 54-57, 1986 | ||
| 1986 | Domestic | Toyonaga, Mitsuyasu, H.Tomotake, Kajitani, Akino | Standardcell CAD system STELLA: Placement program based on Fast Annealing Simulation Method | IEICE Technical Report, CAS85-142,1986, pp.79-84 | |||
| 1986 | Domestic | Toyonaga, Mitsuyasu, H.Tomotake, Kajitani, Akino | Standardcell CAD system STELLA: Chip Floor-Planning | IEICE Technical Report, CAS85-143,1986 | |||
| 1986 | Domestic | M.Toyonaga, T.Akino | Fast Annealing Simulation Method: FAST | SekkeiJidoka34-84,Oct 1986 | |||
| 1986 | Domestic | Mitsuyasu, Tomotake, Toyoanga, Taguchi, Kajita, Akino | STELLA:Automatic Standard-Cell Routing System | Technical Report of IEICE CAS86-80, Sep 1986 | |||
| 1986 | Domestic | Tomotake, Mitsuyasu, Toyonaga, Taguchi, Kajita, Akino | STELLA Database and Database System DBMS | Technical Report of IEICE CAS86-80, Sep 1986 | |||
| 1986 | Magazine | Akino, Kajita, Toyonaga, Mitsuyasu, Tomotake | Full automatic CAD system for Standard-cell LSI layout design | Nikkei-Electronics No400、pp271-298、July 1986 | |||
| 1985 | Inter-national | Yes | Y.Miyatake, M.Toyonaga, M.Yamamoto, O.Nagai | Exact calculation for a three-dimensional classical heisenberg magnet | International Conference on Magnetism, 1985 | ||
| 1985 | Inter-national | Yes | Y.Miyatake, M.Toyonaga, K.Nishio, Y.Yamada, O.Nagai | Phase transition of a three-dimensional quantum heisenberg magnet: Monte carlo simulations | International Conference on Magnetism, 1985 | ||
| 1983 | Inter-national | Yes | O.Nagai, M.Toyonaga, Diefp-The-Hung | Effects of bond disordered in the ising spin glass problem | Journal of Magnetism and Magnetic Materials 31-34, pp.1313-1314, 1983 | ||
| 1981 | Inter-national | Yes | O.Nagai, M.Toyonga | Critical behavior of ising magnets: infinitesimal Migdal-Kadanoff approximation | Journal of physics, C, Solid State Phys., 14, 1981, L545-L549 | ||
| 1980 | Domestic | Yes | Masahiko Toyonaga | Renomirization Group Transform for Ferro-Ising-Magnet-Thin Film | Bussei-Kenkyu, Vol34, No.4, 1980, pp.287-296 | ||